The present disclosure relates to semiconductor structures and methods of forming the same. More particularly, the present disclosure relates to interconnect structures for integrated microelectronic circuits which include a graphene cap located atop at least an uppermost surface of an embedded copper structure and methods of forming the same.
The continuous reduction of active semiconductor device dimensions from one technology node (i.e., generation) to the next necessitates a similar scaling of interconnect structures between neighboring devices (e.g., local wires and vias). One of the problems the semiconductor industry faces as cross-sectional wiring dimensions shrink is the pronounced increase in the electrical resistivity of copper, Cu, interconnects with decreasing linewidths. This increase in electrical resistivity is partly due to the increase in surface and grain boundary scattering, and there is a sharp resistivity increase starting at dimensions comparable to the mean free path of electrons in copper.
Furthermore, the highly resistive diffusion barrier(s) surrounding the Cu body of the interconnect structure contributes significantly to total interconnect resistance, at an increasing proportion as dimensions get smaller. As diffusion barrier thickness is scaled down with metal width to meet conductor effective resistivity goals, copper containment becomes increasing problematic, and eventually new copper passivation techniques and/or diffusion-resistant dielectrics are needed. Otherwise, the diffusion barrier thickness will not be possible to be scaled anymore together with scaling pitch. Obviously, this will have adverse effects on line, and especially, via resistances.